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2000 data sheet 1998 document no. u13415ej2v0ds00 (2nd edition) date published may 2001 n cp(k) printed in japan description the pD780232 is a member of the pD780232 subseries in the 78k/0 series. the pD780232 subseries consists of products that incorporate a vfd controller/driver for panel control. a flash memory version, the pd78f0233, that can operate within the same power supply voltage range as the mask rom version, and various development tools are also under development. detailed function descriptions are provided in the following user? manuals. be sure to read them before designing. pD780232 subseries user? manual: u13364e 78k/0 series user? manual instructions: u12326e features i/o ports: 40 internal rom and ram internal rom: 16 kb internal high-speed ram: 768 bytes internal buffer ram: 32 bytes vfd display ram: 112 bytes minimum instruction execution time can be changed from high speed (0.4 s) to low speed (6.4 s) vfd controller/driver: 53 display outputs (universal grid supported) 8-bit resolution a/d converter: 4 channels serial interface: 2 channels timer: 4 channels power supply voltage: v dd = 4.5 to 5.5 v mos integrated circuit pD780232 8-bit single-chip microcontroller applications monolithic mini components, separated mini components, tuners, cassette tape decks, cd/md players, audio amplifiers, etc. ordering information part number package pD780232gc- -8bt 80-pin plastic qfp (14 14) remark indicates rom code suffix. the mark shows major revised points. the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all devices/types available in every country. please check with local nec representative for availability and additional information.
2 pD780232 data sheet u13415ej2v0ds 78k/0 series lineup the products in the 78k/0 series are listed below. the names enclosed in boxes are subseries names. remark vfd (vacuum fluorescent display) is referred to as fip (fluorescent indicator panel) in some documents, but the functions of the two are the same. pd78054 with added iebus tm controller. emi-noise reduced. 64-pin 64-pin 80-pin 80-pin 80-pin emi-noise reduced version of the pd78054 pd78018f with added uart and d/a converter and enhanced i/o pd780034a pd780988 pd780034ay 64-pin pd780024a with expanded ram capacity pd780024a with enhanced a/d converter on-chip inverter controller and uart. emi-noise reduced. pd78064 pd78064b pd780308 100-pin 100-pin 100-pin pd780308y pd78064y 80-pin 78k/0 series lcd drive pd78064 with enhanced sio, and expanded rom, ram capacity emi-noise reduced version of the pd78064 basic subseries for lcd drive, on-chip uart bus interface supported pd78083 pd78018f pd78018fy pd78014h emi-noise reduced version of the pd78018f basic subseries for control on-chip uart, capable of operating at low voltage (1.8 v) 42-/44-pin 64-pin 64-pin pd78018f with enhanced serial i/o 80-pin pd78054 with enhanced serial i/o 100-pin 100-pin products in mass production products under development y subseries products are compatible with i 2 c bus. pd78054 with added timer and enhanced external interface romless version of the pd78078 100-pin pd78078y with enhanced serial i/o and limited function 100-pin emi-noise reduced version of the pd78078 inverter control pd780208 100-pin vfd drive pd78044f with enhanced i/o and vfd c/d. display output total: 53 pd780208 pd78098b 100-pin pd780024a pd780024ay 80-pin 80-pin pd780852 pd780824 for automobile meter driver. on-chip dcan controller 100-pin pd780958 for industrial meter control on-chip automobile meter controller/driver meter control 80-pin pd780701y on-chip dcan/iebus controller 80-pin pd780833y on-chip controller compliant with j1850 (class 2) pd780948 on-chip dcan controller 64-pin pd780078 pd780078y pd780034a with added timer and enhanced serial i/o pd78054 pd78054y pd78058f pd78058fy pd780058 pd780058y pd78070a pd78070ay pd78078 pd78078y pd780018ay control pd78075b pd780065 pd78044h pD780232 80-pin 80-pin for panel control. on-chip vfd c/d. display output total: 53 pd78044f with added n-ch open-drain i/o. display output total: 34 pd78044f 80-pin basic subseries for vfd drive. display output total: 34 120-pin pd780308 with enhanced display capacity and timer. segment signal output: 40 pins max. pd780318 pd780328 120-pin 120-pin pd780308 with enhanced display capacity and timer. segment signal output: 32 pins max. pd780308 with enhanced display capacity and timer. segment signal output: 24 pins max. pd780338
3 pD780232 data sheet u13415ej2v0ds the major functional differences among the subseries are shown below. function timer 8-bit 10-bit 8-bit serial interface i/o external subseries name 8-bit 16-bit watch wdt a/d a/d d/a expansion control pd78075b 32 k to 40 k 4 ch 1 ch 1 ch 1 ch 8 ch 2 ch 3 ch (uart: 1 ch) 88 1.8 v pd78078 48 k to 60 k pd78070a 61 2.7 v pd780058 24 k to 60 k 2 ch 3 ch (time-division uart: 1 ch) 68 1.8 v pd78058f 48 k to 60 k 3 ch (uart: 1 ch) 69 2.7 v pd78054 16 k to 60 k 2.0 v pd780065 40 k to 48 k 4 ch (uart: 1 ch) 60 2.7 v pd780078 48 k to 60 k 2 ch 8 ch 3 ch (uart: 2 ch) 52 1.8 v pd780034a 8 k to 32 k 1 ch 3 ch (uart: 1 ch) 51 pd780024a 8 ch pd78014h 2 ch 53 pd78018f 8 k to 60 k pd78083 8 k to 16 k 1 ch (uart: 1 ch) 33 inverter pd780988 16 k to 60 k 3 ch note 1 ch 8 ch 3 ch (uart: 2 ch) 47 4.0 v control vfd pd780208 32 k to 60 k 2 ch 1 ch 1 ch 1 ch 8 ch 2 ch 74 2.7 v drive pD780232 16 k to 24 k 3 ch 4 ch 40 4.5 v pd78044h 32 k to 48 k 2 ch 1 ch 1 ch 8 ch 1 ch 68 2.7 v pd78044f 16 k to 40 k 2 ch lcd pd780338 48 k to 60 k 3 ch 2 ch 1 ch 1 ch 10 ch 1 ch 2 ch (uart: 1 ch) 54 1.8 v drive pd780328 62 pd780318 70 pd780308 48 k to 60 k 2 ch 1 ch 8 ch 3 ch (time-division uart: 1 ch) 57 2.0 v pd78064b 32 k 2 ch (uart: 1 ch) pd78064 16 k to 32 k bus pd780948 60 k 2 ch 2 ch 1 ch 1 ch 8 ch 3 ch (uart: 1 ch) 79 4.0 v interface supported pd78098b 40 k to 60 k 1 ch 2 ch 69 2.7 v meter pd780958 48 k to 60 k 4 ch 2 ch 1 ch 2 ch (uart: 1 ch) 69 2.2 v control dash- pd780852 32 k to 40 k 3 ch 1 ch 1 ch 1 ch 5 ch 3 ch (uart: 1 ch) 56 4.0 v board control pd780824 32 k to 60 k 2 ch (uart: 1 ch) 59 note 16-bit timer: 2 channels 10-bit timer: 1 channel v dd min. value rom capacity
4 pD780232 data sheet u13415ej2v0ds function overview item function internal memory rom 16 kb high-speed ram 768 bytes buffer ram 32 bytes vfd display ram 112 bytes general-purpose register 8 bits 32 registers (8 bits 8 registers 4 banks) minimum instruction execution time on-chip minimum instruction execution time variable function 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (@ 5.0 mhz operation with system clock) instruction set multiply/divide (8 bits 8 bits, 16 bits 8 bits) bit manipulation (set, reset, test, boolean operation) i/o ports total: 40 (including alternate-function pins for vfd) cmos i/os: 11 p-ch open-drain i/os: 13 p-ch open-drain outputs: 16 vfd controller/driver total of display outputs: 53 15 ma display current: 20 5 ma display current: 33 a/d converter 8-bit resolution 4 channels power supply voltage: av dd = 4.5 to 5.5 v serial interface 3-wire serial mode (automatic transmit/receive function): 1 channel 2-wire serial mode (transmit only): 1 channel timer 8-bit remote control timer: 1 channel 8-bit timer: 2 channels watchdog timer: 1 channel vectored interrupt maskable internal: 10, external: 2 sources non-maskable internal: 1 software 1 power supply voltage v dd = 4.5 to 5.5 v package 80-pin plastic qfp (14 14)
5 pD780232 data sheet u13415ej2v0ds contents 1. pin configuration (top view) ................................................................................................. 6 2. block diagram ............................................................................................................................. 8 3. pin functions ............................................................................................................................... .9 3.1 port pins ............................................................................................................................... ...................... 9 3.2 non-port pins ............................................................................................................................... ........... 10 3.3 pin i/o circuits and recommended connection of unused pins ................................................... 11 4. memory space ............................................................................................................................. 13 5. peripheral hardware function features ................................................................... 14 5.1 port ............................................................................................................................... ............................. 14 5.2 clock generator ............................................................................................................................... ....... 15 5.3 timer/event counter ............................................................................................................................... 15 5.4 a/d converter ............................................................................................................................... ........... 18 5.5 serial interface ............................................................................................................................... ......... 18 5.6 vfd controller/driver ............................................................................................................................. 19 6. interrupt functions ............................................................................................................... 21 7. standby function ..................................................................................................................... 24 8. reset function ........................................................................................................................... 24 9. mask option ............................................................................................................................... .. 24 10. instruction set .......................................................................................................................... 25 11. electrical specifications .................................................................................................... 28 12. package drawing ...................................................................................................................... 42 13. recommended soldering conditions .............................................................................. 43 appendix a. development tools ............................................................................................... 44 appendix b. related documents .............................................................................................. 47
6 pD780232 data sheet u13415ej2v0ds 1. pin configuration (top view) 80-pin plastic qfp (14 14) pD780232gc- -8bt cautions 1. connect directly the ic (internally connected) pin to v ss1 . 2. connect the av dd pin to v dd1 . 3. connect the av ss pin to v ss1 . remark when the pD780232 is used in application fields that require reduction of the noise from inside the microcontroller, the implementation of noise reduction measures, such as supplying voltage to v dd0 and v dd1 individually and connecting v ss0 and v ss1 to different ground lines, is recommended. 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 v load v dd2 fip20 fip21 fip22 fip23 fip24/p30 fip25/p31 fip26/p32 fip27/p33 fip28/p34 fip29/p35 fip30/p36 fip31/p37 fip32/p40 fip33/p41 fip34/p42 fip35/p43 fip36/p44 fip37/p45 ani1 ani0 v ss0 av dd v dd0 p64/fip52 p63/fip51 p62/fip50 p61/fip49 p60/fip48 p57/fip47 p56/fip46 p55/fip45 p54/fip44 p53/fip43 p52/fip42 p51/fip41 p50/fip40 p47/fip39 p46/fip38 fip0 fip1 fip2 fip3 fip4 fip5 fip6 fip7 fip8 fip9 fip10 fip11 fip12 fip13 fip14 fip15 fip16 fip17 fip18 fip19 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 v dd1 v ss1 x1 x2 ic reset p27/sck1 p26/si1 p25/so1 p24/busy p23 p22 p21/so3 p20/sck3 p00/intp0 p01/intp1 p02/ti av ss ani3 ani2 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
7 pD780232 data sheet u13415ej2v0ds ani0 to ani3: analog input av dd : analog power supply av ss : analog ground busy: busy fip0 to fip52: fluorescent indicator panel ic: internally connected intp0, intp1 external interrupt input p00 to p02: port 0 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p64: port 6 reset: reset sck1, sck3: serial clock si1: serial input so1, so3: serial output ti: timer input v dd0 to v dd2 : power supply v load : negative power supply v ss0 , v ss1 : ground x1, x2: crystal
8 pD780232 data sheet u13415ej2v0ds 2. block diagram 8-bit remote controller timer 9 8-bit timer 80 8-bit timer 81 a/d converter (a/d1) interrupt control (int) serial interface (2-wire mode) serial interface (3-wire mode) watchdog timer 78k/0 cpu core ram 768 bytes rom 16 kb port 0 port 2 port 3 port 4 port 5 port 6 p00 to p02 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p64 system control ti/p02 ani0 to ani3 av dd av ss intp0/p00 busy/p24 so1/p25 so3/p21 si1/p26 sck1/p27 sck3/p20 intp1/p01 fip0 to fip23 fip24/p30 to fip31/p37 fip32/p40 to fip39/p47 fip40/p50 to fip47/p57 fip48/p60 to fip52/p64 vfd controller/ driver v load v dd2 reset x1 x2 v dd0 , v dd1 v ss0 , v ss1 v pp
9 pD780232 data sheet u13415ej2v0ds 3. pin functions 3.1 port pins pin name i/o function after alternate reset function p00 i/o port 0. input intp0 3-bit i/o port. p01 input/output can be specified in 1-bit units. intp1 when used as an input port, an on-chip pull-up resistor can be specified p02 by software. ti p20 i/o port 2. input sck3 p21 8-bit i/o port. so3 p22, p23 input/output can be specified in 1-bit units. p24 when used as an input port, an on-chip pull-up resistor can be specified busy p25 by software. so1 p26 si1 p27 sck1 p30 to p37 output port 3. output fip24 to fip31 p-ch open-drain 8-bit high-tolerance output port. a pull-down resistor can be incorporated in 1-bit units to v load by mask option. p40 to p47 output port 4. output fip32 to fip39 p-ch open-drain 8-bit high-tolerance output port. a pull-down resistor can be incorporated in 1-bit units to v load by mask option. p50 to p57 i/o port 5. input fip40 to fip47 p-ch open-drain 8-bit high-tolerance i/o port. input/output can be specified in 1-bit units. a pull-down resistor can be incorporated in 1-bit units by mask option (connection to v load or v ss0 can be specified in 1-bit units). p60 to p64 i/o port 6. input fip48 to fip52 p-ch open-drain 5-bit high-tolerance i/o port. input/output can be specified in 1-bit units. a pull-down resistor can be incorporated in 1-bit units by mask option (connection to v load or v ss0 can be specified in 1-bit units).
10 pD780232 data sheet u13415ej2v0ds 3.2 non-port pins pin name i/o function after alternate reset function intp0 input external interrupt request input for which the valid edge (rising edge, input p00 intp1 falling edge, or both rising and falling edges) can be specified. p01 ti input 8-bit remote control timer 9 (tm9) timer input input p02 sck3 i/o serial interface serial clock input/output input p20 so3 output serial interface serial data output input p21 busy input serial interface automatic transmit/receive busy signal input input p24 so1 output serial interface serial data output input p25 si1 input serial interface serial data input input p26 sck1 i/o serial interface serial clock input/output input p27 fip0 to fip23 output vfd controller/driver high-tolerance large current output. output fip24 to fip31 a pull-down resistor can be incorporated to v load in 1-bit units by a mask p30 to p37 fip32 to fip39 option. p40 to p47 fip40 to fip47 input p50 to p57 fip48 to fip52 p60 to p64 v load connecting pull-down resistor for vfd controller/driver reset input system reset input x1 input connecting crystal resonator for system clock oscillation x2 ani0 to ani3 input a/d converter analog input input av dd a/d converter analog power supply/reference voltage input. make the same potential as v dd1 . av ss a/d converter ground potential. make the same potential as v ss1 . v dd0 positive power supply for ports v dd1 positive power supply except for ports, analog block, and vfd controller/driver v dd2 positive power supply for vfd controller/driver v ss0 ground potential for ports v ss1 ground potential except for ports and analog block ic internally connected. connect directly to v ss1 . vfd controller/driver high-tolerance large current output. a pull-down resistor can be incorporated in 1-bit units by a mask option (connection to v load or v ss0 can be specified in 1-bit units).
11 pD780232 data sheet u13415ej2v0ds 3.3 pin i/o circuits and recommended connection of unused pins the i/o circuit type of each pin and the recommended connection of unused pins are shown in table 3-1. for the i/o circuit configuration of each type, see figure 3-1 . table 3-1. types of pin i/o circuits pin name i/o circuit type i/o recommended connection of unused pins p00/intp0 8-c i/o input: independently connect to v ss0 via a resistor. p01/intp1 output: leave open. p02/ti p20/sck3 input: independently connect to v dd0 or v ss0 via a resistor. p21/so3 output: leave open. p22, p23 p24/busy p25/so1 p26/si1 p27/sck1 p30/fip24 to p37/fip31 14-f output leave open. p40/fip32 to p47/fip39 p50/fip40 to p57/fip47 15-d i/o input: independently connect to v dd0 or v ss0 via a resistor. p60/fip48 to p64/fip52 output: leave open. fip0 to fip23 14-f output leave open. reset 2 input ani0 to ani3 7 connect to v dd0 or v ss0 . av dd connect to v dd1 . av ss connect to v ss1 . v load ic connect directly to v ss1 .
12 pD780232 data sheet u13415ej2v0ds figure 3-1. pin i/o circuits type 2 type 7 type 8-c in schmitt-triggered input with hysteresis characteristics v dd0 p-ch in/out p-ch v dd0 pullup enable data output disable n-ch v ss0 data v dd0 p-ch n-ch v dd0 p-ch out mask option ? ? ? ? ? ? ? ? p-ch n-ch in
13 pD780232 data sheet u13415ej2v0ds 4. memory space the memory map of the figure 4-1. memory map reserved data memory space program memory space special function registers (sfr) 256
14 pD780232 data sheet u13415ej2v0ds 5. peripheral hardware function features 5.1 port there are three kinds of i/o ports. ?cmos i/o (ports 0, 2): 11 ?p-ch open-drain output (ports 3, 4): 16 ?p-ch open-drain i/o (ports 5, 6): 13 total: 40 table 5-1. port functions name pin name function port 0 p00 to p02 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip resistor can be specified by software. port 2 p20 to p27 i/o port. input/output can be specified in 1-bit units. when used as an input port, an on-chip resistor can be specified by software. port 3 p30 to p37 p-ch open-drain high-tolerance output port. a pull-down resistor can be incorporated in 1-bit units to v load by a mask option. port 4 p40 to p47 p-ch open-drain high-tolerance output port. a pull-down resistor can be incorporated in 1-bit units to v load by a mask option. port 5 p50 to p57 p-ch open-drain high-tolerance i/o port. input/output can be specified in 1-bit units. a pull-down resistor can be incorporated in 1-bit units by a mask option (connection to v load or v ss0 can be specified in 1-bit units ). port 6 p60 to p64 p-ch open-drain high-tolerance i/o port. input/output can be specified in 1-bit units. a pull-down resistor can be incorporated in 1-bit units by a mask option (connection to v load or v ss0 can be specified in 1-bit units).
15 pD780232 data sheet u13415ej2v0ds 5.2 clock generator the minimum instruction execution time can be changed. 0.4 s/0.8 s/1.6 s/3.2 s/6.4 s (@ 5.0 mhz operation with main system clock) figure 5-1. clock generator block diagram 5.3 timer/event counter four timer/event counter channels are incorporated. 8-bit remote control timer: 1 channel 8-bit timer: 2 channels watchdog timer: 1 channel table 5-2. timer/event counter operations 8-bit remote control timer 8-bit timer watchdog timer operation interval timer 2 channels 1 channel mode function pulse width measurement 1 input interrupt source 3 2 1 main system clock oscillator x1 prescaler selector standby controller f x stop cpu clock (f cpu ) clock to peripheral hardware x2 f x 2 4 f x 2 3 f x 2 2 f x 2 prescaler
16 pD780232 data sheet u13415ej2v0ds figure 5-2. block diagram of 8-bit remote control timer (tm9) figure 5-3. block diagram of 8-bit timer (tm80) selector/controller f x f x /2 2 f x /2 4 f x /2 6 8-bit timer counter 80 (tm80) 8-bit compare register 80 (cr80) internal bus match inttm80 internal bus 8-bit capture register 90 (cp90) 8-bit capture register 91 (cp91) 8-bit timer counter 9 (tm9) 1/2 inttm90 inttm91 inttm92 ti/p02 selector f x /2 6 f x /2 7 f x /2 8 f x /2 9 noise elimination rising edge detector noise elimination falling edge detector internal bus
17 pD780232 data sheet u13415ej2v0ds figure 5-4. block diagram of 8-bit timer (tm81) figure 5-5. watchdog timer block diagram oscillation stabilization time selection register (osts) clock input controller intwdt reset wdt mode signal 3 osts2 osts1 osts0 wdcs2 wdcs1 wdcs0 internal bus divider divided clock selector output controller division mode selector run wdtm4 wdtm3 watchdog timer clock selection register (wdcs) watchdog timer mode register (wdtm) run f x /2 8 f x selector/controller f x /2 f x /2 3 f x /2 5 f x /2 7 8-bit timer counter 81 (tm81) 8-bit compare register 81 (cr81) internal bus match inttm81
18 pD780232 data sheet u13415ej2v0ds 5.4 a/d converter an 8-bit resolution 4-channel a/d converter is incorporated. a/d conversion can be started by software only. figure 5-6. a/d converter block diagram internal bus selector serial clock counter serial clock controller interrupt request signal generator si1/p26 so1/p25 sck1/p27 f x /2 2 to f x /2 4 intcsi1 busy/p24 automatic data transmit/receive address pointer (adtp) buffer ram serial shift register 1 (sio1) match automatic data transmit/receive transfer interval specification register (adti) 5-bit counter handshake controller 5.5 serial interface two clocked serial interface channels are incorporated. serial interface sio1 operates in the 3-wire serial mode (with automatic transmit/receive function), in which msb first/lsb first switching is possible. serial interface sio3 operates in the 2-wire serial mode (transmit only) in which the first bit is fixed to msb. figure 5-7. serial interface sio1 block diagram ani0 ani1 ani2 ani3 intad selector sample & hold circuit internal bus a/d converter (8 bits) a/d conversion result register (adcr0)
19 pD780232 data sheet u13415ej2v0ds figure 5-8. serial interface sio3 block diagram 5.6 vfd controller/driver a vfd controller/driver with the following functions is incorporated. (a) total number of display outputs: 53. output of 16 patterns is enabled. (b) 112-byte display ram is provided to enable display signal output by reading display data automatically (direct memory access (dma)). (c) a port pin that is not used for vfd display can be used as an output port or an i/o port (except for fip0 to fip23, which are vfd output-only pins). (d) the luminance can be adjusted in 8 levels using display mode register 1 (dspm1). (e) hardware taking into consideration the key scan application is incorporated. (f) whether the key scan timing is inserted or not is selectable. (g) a high-tolerance output buffer (vfd driver) that can drive the vfd directly is incorporated. (h) vfd output pins can incorporate a pull-down resistor, set by a mask option. f x /2 2 to f x /2 4 intcsi3 so3/p21 sck3/p20 selector internal bus serial shift register 3 (sio3) serial clock counter interrupt request signal generator serial clock controller
20 pD780232 data sheet u13415ej2v0ds figure 5-9. vfd controller/driver block diagram internal bus display data memory display data selector port output latch high-tolerance buffer fip0 fip24/p30 fip52/p64 display data latch
21 pD780232 data sheet u13415ej2v0ds 6. interrupt functions there are 3 types of interrupt functions. non-maskable: 1 maskable: 12 software: 1 table 6-1. interrupt source list interrupt default interrupt source internal/ vector basic table configuration type priority note 1 name trigger external address type note 2 non- intwdt watchdog timer overflow (when watchdog timer internal 0004h (a) maskable mode 1 is selected) maskable 0 intwdt watchdog timer overflow (when interval timer (b) mode is selected) 1 intp0 pin input edge detection external 0006h (c) 2 intp1 0008h 3 inttm90 remote control timer input rising edge detection internal 000ah (b) 4 inttm91 remote control timer input falling edge detection 000ch 5 inttm92 remote control timer overflow 000eh 6 intks key scan timing from vfd controller/driver 0010h 7 intcsi1 serial interface sio1 transfer end 0012h 8 intcsi3 serial interface sio3 transfer end 0014h 9 inttm80 tm80 and cr80 match 0016h 10 inttm81 tm81 and cr81 match 0018h 11 intad a/d conversion end 001ah software brk brk instruction execution 003eh (d) notes 1. default priority is the priority order when more than one maskable interrupt request is generated simultaneously. 0 is the highest priority and 11 is the lowest. 2. basic configuration types (a) to (d) correspond to (a) to (d) in figure 6-1. remark two watchdog timer interrupt sources (intwdt) are available: a non-maskable interrupt and a maskable interrupt (internal), either of which can be selected.
22 pD780232 data sheet u13415ej2v0ds figure 6-1. basic interrupt function configuration (1/2) (a) internal non-maskable interrupt (c) external maskable interrupt (intp0, intp1) (b) internal maskable interrupt internal bus priority controller vector table address generator standby release signal interrupt request internal bus mk ie pr isp if priority controller vector table address generator standby release signal interrupt request internal bus ie pr isp mk if edge detector external interrupt rising/falling edge enable register (egp, egn) priority controller vector table address generator standby release signal internal request
23 pD780232 data sheet u13415ej2v0ds figure 6-1. basic interrupt function configuration (2/2) (d) software interrupt internal bus interrupt request vector table address generator priority controller
24 pD780232 data sheet u13415ej2v0ds 7. standby function the standby function is a function to reduce the current consumption. the following two types of standby functions are available. halt mode: halts the cpu operating clock and enables a reduction in the average current consumption by intermittent operation with normal operation. stop mode: halts the system clock oscillation. halts all operations with the system clock and sets an ultra- low power consumption state. figure 7-1. standby function 8. reset function the following two types of resetting methods are available. external reset by the reset input internal reset by watchdog timer loop detection 9. mask option the mask options for the pD780232 are shown in table 9-1. table 9-1. pin mask option selection system clock operation halt mode (clock supply to cpu is stopped, and oscillation is maintained) stop instruction interrupt request interrupt request halt instruction stop mode (system clock oscillation is stopped) pin name mask option fip 0 to fip23, an on-chip pull-down resistor can be specified for v load in 1-bit units. p30/fip24 to p37/fip31, p40/fip32 to p47/fip39 p50/fip40 to p57/fip47, an on-chip pull-down resistor can be specified for v load or v ss0 in 1-bit units. p60/fip48 to p64/fip52
25 pD780232 data sheet u13415ej2v0ds 10. instruction set (1) 8-bit instructions mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, ror4, rol4, push, pop, dbnz 2nd operand [hl+byte] #byte a r note sfr saddr !addr16 psw [de] [hl] [ hl+b] $addr16 1 none 1st operand [hl+c] a add mov mov mov mov mov mov mov mov ror addc xch xch xch xch xch xch xch rol sub add add add add add rorc subc addc addc addc addc addc rolc and sub sub sub sub sub or subc subc subc subc subc xor and and and and and cmp or or or or or xor xor xor xor xor cmp cmp cmp cmp cmp r mov mov inc add dec addc sub subc and or xor cmp b, c dbnz sfr mov mov saddr mov mov dbnz inc add dec addc sub subc and or xor cmp !addr16 mov psw mov mov push pop [de] mov [hl] mov ror4 rol4 [hl+byte] mov [hl+b] [hl+c] x mulu c divuw note except r = a
26 pD780232 data sheet u13415ej2v0ds (2) 16-bit instructions movw, xchw, addw, subw, cmpw, push, pop, incw, decw 2nd operand #word ax rp note sfrp saddrp !addr16 sp none 1st operand ax addw movw movw movw movw movw subw xchw cmpw rp movw movw note incw decw push pop sfrp movw movw saddrp movw movw !addr16 movw sp movw movw note only when rp = bc, de, hl (3) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr 2nd operand a.bit sfr.bit saddr.bit psw.bit [hl].bit cy $addr16 none 1st operand a.bit mov1 bt set1 bf clr1 btclr sfr.bit mov1 bt set1 bf clr1 btclr saddr.bit mov1 bt set1 bf clr1 btclr psw.bit mov1 bt set1 bf clr1 btclr [hl].bit mov1 bt set1 bf clr1 btclr cy mov1 mov1 mov1 mov1 mov1 set1 and1 and1 and1 and1 and1 clr1 or1 or1 or1 or1 or1 not1 xor1 xor1 xor1 xor1 xor1
27 pD780232 data sheet u13415ej2v0ds (4) call instruction/branch instructions call, callf, callt, br, bc, bnc, bz, bnz, bt, bf, btclr, dbnz 2nd operand ax !addr16 !addr11 [addr5] $addr16 1st operand basic instruction br call callf callt br br bc bnc bz bnz compound instruction bt bf btclr dbnz (5) other instructions adjba, adjbs, brk, ret, reti, retb, sel, nop, ei, di, halt, stop
28 pD780232 data sheet u13415ej2v0ds 11. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ?.3 to +6.5 v v load v dd ?45 to v dd + 0.3 v av dd ?.3 to v dd + 0.3 v av ss ?.3 to +0.3 v input voltage v i1 p00 to p02, p20 to p27, x1, x2, reset ?.3 to v dd + 0.3 v v i2 p50 to p57, p60 to p64 p-ch open drain v dd ?45 to v dd + 0.3 v output voltage v o1 ?.3 to v dd + 0.3 v v o2 v dd ?45 to v dd + 0.3 v analog input voltage v an ani0 to ani3 analog input pins av ss to av dd v output current, high i oh per pin for p00 to p02 and p20 to p27 ?0 ma total for p00 to p02 and p20 to p27 ?0 ma per pin for fip0 to fip23, p30 to p37, p40 to p47, ?0 ma p50 to p57, and p60 to p64 total for fip0 to fip23, p30 to p37, p40 to p47, peak value ?00 ma p50 to p57, and p60 to p64 rms value ?20 ma output current, low i ol note 1 per pin for p00 to p02 and p20 to p27 peak value 10 ma rms value 5 ma total for p00 to p02 and p20 to p27 peak value 20 ma rms value 10 ma total power p t note 2 t a = ?0 to +60 c 700 mw dissipation t a = +60 to +85 c 500 mw operating ambient t a ?0 to +85 c temperature storage temperature t stg ?0 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. notes 1. the rms value should be calculated as follows: [rms value] = [peak value] duty
29 pD780232 data sheet u13415ej2v0ds notes 2. the allowable total power dissipation differs depending on the temperature (see the following figure). how to calculate total power dissipation the power consumption of the pD780232 can be divided to the following three types. the sum of the three power consumption types should be less than the total power dissipation p t (80% or less of ratings is recommended). <1> cpu power consumption: calculate v dd (max.) i dd (max.). <2> output pin power consumption: power consumption when maximum current flows to vfd output pins. <3> pull-down resistor power consumption: power consumption by the pull-down resistors incorporated in the vfd output pins by a mask option. the following shows how to calculate total power consumption for the example in figure 11-1. example assume the following conditions: v dd = 5.5 v, 5.0 mhz oscillation supply current (i dd ) = 21.0 ma vfd output: 11 grids 10 segments (blanking width = 1/16) the maximum current at the grid pin is 15 ma. the maximum current at the segment pin is 5 ma. at the key scan timing, the vfd output pin is off. vfd output voltage: grids v od = v dd ?2 v (voltage drop of 2 v) segments v od = v dd ?0.5 v (voltage drop of 0.5 v) fluorescent display control voltage (v load ) = ?5 v mask option pull-down resistor = 35 k ? +80 +40 0 40 800 600 500 400 200 temperature [ ? c] +85 total power dissipation p t [mw]
30 pD780232 data sheet u13415ej2v0ds by placing the above conditions in calculations <1> to <3>, the total dissipation can be calculated. <1> cpu power consumption: 5.5 v 21.0 ma = 115.5 mw <2> output pin power consumption: grid (v dd v od ) total current value of each grid (1 blanking width) number of grids + 1 =2 v 15 ma 11 grids (1 1 ) = 25.8 mw 11 grids + 1 16 segment (v dd v od ) total segment current value of illuminated dots (1 blanking width) number of grids +1 = 0.5 v 5 ma 31 dots (1 1 ) = 6.1 mw 11 grids + 1 16 <3> pull-down resistor power consumption: grid (v od v load ) 2 number of grids (1 blanking width) pull-down resistor value number of grids + 1 = (5.5 v 2 v ( 35 v)) 2 11 grids (1 1 ) = 36.4 mw 35 k ? 11 grids + 1 16 segment (v od v load ) 2 number of illuminated dots (1 blanking width) pull-down resistor value number of grids + 1 = (5.5 v 0.5 v ( 35 v)) 2 31 dots (1 1 ) = 110.7 mw 35 k ? 11 grids + 1 16 total power consumption = <1> + <2> + <3> = 115.5 + 25.8 + 6.1 + 36.4 + 110.7 = 294.5 mw in this example, the total power consumption does not exceed the rating of the allowable total power dissipation, so there is no problem in the power consumption. however, when the total power consumption exceeds the rating of the total power dissipation, it is necessary to lower the power consumption. to reduce the power consumption, reduce the number of pull-down resistors.
31 pD780232 data sheet u13415ej2v0ds figure 11-1. display example of 10 segments-11 digits 012 34 567 8910 i j i am pm sun mon tue wed thu fri sat j j a g d b c f e j ihgfedcba 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (vfd output pin: fip0 to fip20) t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 h display data memory 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 fa02h, fa01h, fa00h fa09h, fa08h, fa07h fa10h, fa0fh, fa0eh fa17h, fa16h, fa15h fa1eh, fa1dh, fa1ch fa25h, fa24h, fa23h fa2ch, fa2bh, fa2ah fa33h, fa32h, fa31h fa3ah, fa39h, fa38h fa41h, fa40h, fa3fh fa48h, fa47h, fa46h
32 pD780232 data sheet u13415ej2v0ds system clock oscillator characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) resonator recommended circuit parameter conditions min. typ. max. unit ceramic resonator oscillation frequency v dd = oscillation 1 5 mhz (f x ) note 1 voltage range oscillation stabilization after v dd reaches 4 ms time note 2 the minimum value of oscillation voltage range crystal resonator oscillation frequency 1 5 mhz (f x ) note 1 oscillation stabilization 10 ms time note 2 external clock x1 input frequency 1 5 mhz (f x ) note 1 x1 input high-/low-level 85 450 ns width (t xh /t xl ) notes 1. indicates only oscillator characteristics. refer to ac characteristics for instruction execution time. 2. time required to stabilize oscillation after reset or stop release. caution when using the system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with the other signal lines. do not route the wiring near a signal line through which a high fluctuating current flows. always make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern through which a high current flows. do not fetch signals from the oscillator. x1 x2 pd74hcu04 x1 x2 v ss1 c1 c2 x1 x2 v ss1 c1 c2
33 pD780232 data sheet u13415ej2v0ds recommended oscillator constant system clock: ceramic resonator (t a = ?0 to +85 c) manufacturer part number frequency recommended circuit constant oscillation voltage range (mhz) c1 (pf) c2 (pf) min. (v) max. (v) murata mfg. csb 1000j 1.00 150 150 4.5 5.5 co., ltd. csa2.00mg040 2.00 100 100 cst2.00mg040 on-chip on-chip csa3.58mg 3.58 30 30 cst3.58mgw on-chip on-chip csts0358mg06 csa4.19mg 4.19 30 30 cst4.19mgw on-chip on-chip csts0419mg06 csa5.00mg 5.00 30 30 cst5.00mgw on-chip on-chip csts0500mg03 caution the oscillator constant and oscillation voltage range indicate conditions of stable oscillation. oscillation frequency precision is not guaranteed. for applications requiring oscillation fre- quency precision, the oscillation must be adjusted on the implementation circuit. for details, please contact directly the manufacturer of the resonator you will use.
34 pD780232 data sheet u13415ej2v0ds capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c in f = 1 mhz p00 to p02, p20 to p27 15 pf unmeasured pins returned to 0 v p50 to p57, p60 to p64 35 pf output capacitance c out f = 1 mhz p00 to p02, p20 to p27 15 pf unmeasured pins returned to 0 v p30 to p37, p40 to p47, 35 pf p50 to p57, p60 to p64, fip0 to fip23 i/o c io f = 1 mhz p00 to p02, p20 to p27 15 pf capacitance unmeasured pins returned to 0 v p50 to p57, p60 to p64 35 pf dc characteristics (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit input voltage, high v ih1 p00 to p02, p20 to p27, reset 0.7v dd v dd v v ih2 p50 to p57, p60 to p64 0.7v dd v dd v v ih3 x1, x2 v dd ?0.5 v dd v input voltage, low v il1 p00 to p02, p20 to p27, reset 0 0.2v dd v v il2 x1, x2 0 0.4 v output voltage, high v oh i oh = ? ma v dd ?1.0 v dd v i oh = ?00 av dd ?0.5 v dd v output voltage, low v ol p00 to p02, p20 to p27 i ol = 400 a 0.5 v input leakage i lih1 p00 to p02, p20 to p27, p50 to p57, p60 to p64, reset v in = v dd 3 a current, high i lih2 x1, x2 20 a input leakage i lil1 p00 to p02, p20 to p27, reset v in = 0 v 3 a current, low i lil2 x1, x2 ?0 a i lih3 p50 to p57, p60 to p64 v in = v load = v dd ?40 v ?0 a output leakage i loh p00 to p02, p20 to p27, p30 to p37, v out = v dd 3 a current, high p40 to p47, p50 to p57, p60 to p64 output leakage i lol1 p00 to p02, p20 to p27 v out = 0 v 3 a current, low i lol2 p30 to p37, p40 to p47, p50 to p57, p60 to p64 v out = v load = v dd ?40 v ?0 a vfd output current i od fip0 to fip19 v od = v dd ?2 v 15 ma fip20 to fip52 ? ma software pull-up r 1 p00 to p02, p20 to p27 v in = 0 v 10 30 100 k ? resistance on-chip mask option r 2 p50 to p57, p60 to p64 15 35 90 k ? pull-down resistance (v ss0 connection) on-chip mask option r 3 fip0 to fip52 v od ?v load 30 60 135 k ? pull-down resistance = 40 v (v load connection) power supply i dd1 5 mhz crystal oscillation operation mode pcc = 00h 7 14 ma current note i dd2 5 mhz crystal oscillation halt mode 1.5 4.5 ma i dd3 stop mode 1 30 a note refers to the current flowing to the v dd pin. the current flowing to the on-chip pull-up and pull-down resistors is not included. remarks 1. unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 2. pcc: processor clock control register
35 pD780232 data sheet u13415ej2v0ds ac characteristics (1) basic operation (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit cycle time t cy operated with main system clock 0.4 32 s (minimum instruction execution time) interrupt request t inth intp0, intp1 10 s input high-/low-level t intl width reset low-level t rsl 10 s width t cy vs. v dd (2) timer/counter (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) parameter symbol conditions min. typ. max. unit ti input high-/ t tih 2/f count + 0.2 note s low-level width t til note f count is the frequency of the count clock selected by tm9 (the frequency can be selected from f x /2 6 , f x /2 7 , f x /2 8 , and f x /2 9 ). 123456 0 0.4 0.5 1.0 2.0 10 60 cycle time t cy ( s) supply voltage v dd (v) 30 guaranteed operating range
36 pD780232 data sheet u13415ej2v0ds (3) serial interface (t a = ?0 to +85 c, v dd = 4.5 to 5.5 v) (a) serial interface (3-wire serial mode) (i) 3-wire serial mode (sck1: internal clock output) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy1 800 ns sck1 high-/low-level t kh1 t kcy1 /2 50 ns width t kl1 si1 setup time t sik1 100 ns (to sck1 ) si1 hold time t ksi1 400 ns (from sck1 ) delay time from sck1 t kso1 c = 100 pf note 300 ns to so1 output note c is the load capacitance of the sck1 and so1 output lines. (ii) 3-wire serial mode (sck1: external clock input) parameter symbol conditions min. typ. max. unit sck1 cycle time t kcy2 800 ns sck1 high-/low- t kh2 400 ns level width t kl2 si1 setup time t sik2 100 ns (to sck1 ) si1 hold time t ksi2 400 ns (from sck1 ) delay time from sck1 t kso2 c = 100 pf note 300 ns to so1 output sck1 rise/fall time t r2 1 s t f2 note c is the load capacitance of the so1 output line.
37 pD780232 data sheet u13415ej2v0ds (b) serial interface (2-wire serial mode) (i) 2-wire serial mode (sck3?nternal clock output) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy3 800 ns sck3 high-/low-level t kh3 t kcy3 /2 50 ns width t kl3 delay time from sck3 t kso3 c = 100 pf note 300 ns to so3 output note c is the load capacitance of the sck3 and so3 output lines. (ii) 2-wire serial mode (sck3?xternal clock input) parameter symbol conditions min. typ. max. unit sck3 cycle time t kcy4 800 ns sck3 high-/low- t kh4 400 ns level width t kl4 delay time from sck3 t kso4 c = 100 pf note 300 ns to so3 output sck3 rise/fall time t r4 1 s t f4 note c is the load capacitance of the so3 output line.
38 pD780232 data sheet u13415ej2v0ds ac timing test points (excluding x1 input) clock timing ti timing test points 0.8v dd 0.2v dd 0.8v dd 0.2v dd x1 input 0.4 v (max.) v dd 0.5 v (min.) t xl t xh 1/f x ti t til t tih
39 pD780232 data sheet u13415ej2v0ds serial transfer timing 3-wire serial mode: 2-wire serial mode: a/d converter characteristics (t a = ?0 to +85 c, av dd = v dd = 4.0 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit overall error note 1 1.0 % conversion time note 2 t conv 14 s analog input voltage v ian av ss av dd v notes 1. quantization error ( 1/2lsb) is not included. this parameter is indicated as the ratio to the full-scale value. 2. set the a/d conversion time to 14 s or more. sck1 si1 so1 input data output data t r2 t f2 t sik1, 2 t kl1, 2 t kcy1, 2 t kh1, 2 t ksi1, 2 t kso1, 2 t kcy3,4 t kso3,4 sck3 so3 t kh3,4 t f4 t r4 t kl3,4
40 pD780232 data sheet u13415ej2v0ds data memory stop mode low supply voltage data retention characteristics (t a = ?0 to +85 c) parameter symbol conditions min. typ. max. unit data retention v dddr 2.0 5.5 v supply voltage data retention i dddr 0.1 30 a supply current release signal t srel 0 s set time oscillation stabili- t wait release by reset 2 17 /f x ms zation wait time release by interrupt request note ms note 2 12 /f x , 2 14 /f x to 2 17 /f x can be selected by bits 0 to 2 (osts0 to osts2) of the oscillation stabilization time select register (osts). data retention timing (stop mode release by reset) data retention timing (standby release signal: stop mode release by interrupt request signal) data retention mode reset v dd stop mode stop instruction execution v dddr operating mode internal reset operation halt mode t srel t wait data retention mode v dd stop mode stop instruction execution v dddr operating mode halt mode t srel t wait standby release signal (interrupt request)
41 pD780232 data sheet u13415ej2v0ds interrupt request input timing reset input timing t intl t inth intp0, intp1 t rsl reset
42 pD780232 data sheet u13415ej2v0ds 12. package drawing 80-pin plastic qfp (14x14) note each lead centerline is located within 0.13 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 17.20 0.20 14.00 0.20 0.13 0.825 i 17.20 0.20 j c 14.00 0.20 h 0.32 0.06 0.65 (t.p.) k 1.60 0.20 p 1.40 0.10 q 0.125 0.075 l 0.80 0.20 f 0.825 n 0.10 m 0.17 + 0.03 ? 0.07 p80gc-65-8bt-1 s 1.70 max. r3 + 7 ? 3 41 60 40 61 21 80 20 1 s s n j detail of lead end c d a b r k m l p i s q g f m h
43 data sheet u13415ej2v0ds 13. recommended soldering conditions the pD780232 should be soldered and mounted under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact an nec sales representative. table 13-1. surface mounting type soldering conditions soldering soldering conditions recommended method condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or ir35-00-2 higher), count: two times or less vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or vp15-00-2 higher), count: two times or less wave soldering solder bath temperature: 260 c max., time: 10 seconds max., count: once, ws60-00-1 preheating temperature: 120 c max. (package surface temperature) partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) caution do not use different soldering methods together (except for partial heating).
44 pD780232 data sheet u13415ej2v0ds appendix a. development tools the following development tools are available for system development using the pD780232. also refer to (6) notes on using development tools . (1) software package sp78k0 software package common to 78k/0 series (2) language processing software ra78k0 assembler package common to 78k/0 series cc78k0 c compiler package common to 78k/0 series df780233 device file for pD780232 subseries cc78k0-l c compiler library source file common to 78k/0 series (3) flash memory writing tools flashpro iii dedicated flash programmer for on-chip flash memory microcontrollers (fl-pr3, pg-fp3) fa-80gc adapter for flash memory writing. used by connecting to flashpro iii. ?for 80-pin plastic qfp (gc-8bt type) (4) debugging tools when in-circuit emulator ie-78k0-ns(-a) is used ie-78k0-ns(-a) in-circuit emulator common to 78k/0 series ie-70000-mc-ps-b power supply unit for ie-78k0-ns ie-78k0-ns-pa performance board to enhance/extend the functions of the ie-78k0-ns ie-70000-98-if-c adapter required when pc-9800 series (except notebook type) is used as host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable required when notebook-type pc is used as host machine (pcmcia socket supported) ie-70000-pc-if-c adapter required when ibm pc/at compatible is used as host machine (isa bus supported) ie-70000-pci-if-a adapter required when pc incorporating pci bus is used as host machine ie-780233-ns-em4, emulation board and i/o board to emulate the pD780232 subseries ie-78k0-ns-p01 np-80gc emulation probe for 80-pin plastic qfp (gc-8bt type) np-80gc-tq np-h80gc-tq ev-9200gc-80 conversion socket to connect the np-80gc and the target system board on which 80-pin plastic qfp (gc-8bt type) can be mounted tgc-080sbp conversion adapter to connect the np-80gc-tq or np-h80gc-tq and the target system board on which 80-pin plastic qfp (gc-8bt type) can be mounted id78k0-ns integrated debugger for ie-78k0-ns sm78k0 system simulator common to 78k/0 series df780233 device file for pD780232 subseries
45 pD780232 data sheet u13415ej2v0ds when in-circuit emulator ie-78001-r-a is used ie-78001-r-a in-circuit emulator common to 78k/0 series ie-70000-98-if-c adapter required when pc-9800 series (except notebook type) is used as host machine (c bus supported) ie-70000-pc-if-c adapter required when ibm pc/at compatible is used as host machine (isa bus supported) ie-70000-pci-if-a adapter required when pc incorporating pci bus is used as host machine ie-70000-r-sv3 interface adapter and cable required when ews is used as host machine ie-780233-ns-em4, emulation board and i/o board to emulate the pD780232 subseries ie-78k0-ns-p01 ie-78k0-r-ex1 emulation probe conversion board required when using ie-780232-ns-em1 on ie-78001-r-a ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-8bt type) ev-9200gc-80 conversion socket to connect the ep-78230gc-r and the target system board on which 80-pin plastic qfp (gc-8bt type) can be mounted id78k0 integrated debugger for ie-78001-r-a sm78k0 system simulator common to 78k/0 series df780233 device file for pD780232 subseries (5) real-time oss rx78k0 real-time os for 78k/0 series mx78k0 os for 78k/0 series
46 pD780232 data sheet u13415ej2v0ds (6) notes on using development tools the id78k0-ns, id78k0, and sm78k0 are used in combination with the df780233. the cc78k0 and rx78k0 are used in combination with the ra78k0 and df780233. the fl-pr3, fa-80gc, np-80gc, np-80gc-tq, and np-h80gc-tq are products of naito densei machida mfg. co., ltd (+81-45-475-4191). the tgk-080sbp is a product made by tokyo eletech corporation. for further information, contact: daimaru kogyo, ltd. tokyo electronics department (tel +81-3-3820-7112) osaka electronics department (tel +81-6-6244-6672) for third-party development tools, see the single-chip microcontroller development tool selection guide (u11069e) . the host machines and os suitable for each software are as follows: host machine pc ews [os] pc-9800 series [japanese windows] hp9000 series 700 [hp-ux] ibm pc/at compatibles sparcstation [sunos, solaris] software [japanese/english windows] ra78k0 note cc78k0 note id78k0-ns id78k0 sm78k0 rx78k0 note mx78k0 note note dos-based software
47 pD780232 data sheet u13415ej2v0ds appendix b. related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. documents related to devices document name document no. pD780232 subseries user? manual u13364e pD780232 data sheet this manual pd78f0233 data sheet u13322e 78k/0 series instructions user's manual u12326e 78k/0, 78k/0s series flash memory write application note u14458e documents related to development tools (user? manuals) document name document no. ra78k0 assembler package operation u14445e language u14446e structured assembly language u11789e cc78k0 c compiler operation u14297e language u14298e pg-fp3 flash memory programmer u13502e ie-78k0-ns in-circuit emulator u13731e ie-78k0-ns-a in-circuit emulator u14889e ie-78001-r-a in-circuit emulator u14142e ie-78k0-r-ex1 in-circuit emulator to be prepared ie-780233-ns-em4 emulation board u14666e ep-78230 emulation probe eeu-1515 sm78k0s, sm78k0 system simulator operation u14611e ver. 2.10 or later windows based sm78k series system simulator ver. 2.10 or later external parts user open u15006e interface specifications id78k0-ns integrated debugger ver. 2.00 or later operation u14379e windows based id78k0-ns, id78k0s-ns integrated debugger operation u14910e ver. 2.20 or later windows based id78k0 integrated debugger windows based guide u11649e reference u11539e
48 pD780232 data sheet u13415ej2v0ds documents related to embedded software (user? manuals) document name document no. 78k/0 series real-time os fundamentals u11537e installation u11536e 78k/0 series os mx78k0 fundamentals u12257e other documents document name document no. semiconductor selection guide - products & package - (cd-rom) x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability/quality control system c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892e caution the related documents listed above are subject to change without notice. be sure to use the latest version of each document for designing.
49 pD780232 data sheet u13415ej2v0ds [memo]
50 pD780232 data sheet u13415ej2v0ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. fip and iebus are trademarks of nec corporation. windows is either a registered trademark or trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc.
51 pD780232 data sheet u13415ej2v0ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
pD780232 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. m8e 00.4 the information in this document is current as of february, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a pa rticular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

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